No clocks
---------

Each plugged-in circuit must provide a "ready" bit to say when it has data available to transmit, or is ready to receive new data. The instruction "A -> B" cannot proceed until A is ready to provide data, and cannot end until B is ready to accept data and has accepted it.

For example, examine the first three lines of the previous example:

   5 -> 82      // slot 5 to adder
   6 -> 82      // slot 6 to adder
   82 -> 95     // adder -> multiplier

Assuming that everything here was idle before we started, and all ready bits were true, the first two instructions above will have no wait and will run at the maximum speed of the WIZ's bus copy cycle, more than 100 GHz or 10 ps per cycle (a 2020 estimate, surely much faster today).

(I will continue to use "10 ps" here to indicate "the time for a slot-to-slot bus copy instruction when everything is ready in advance". It is the fastest the processor can cycle.)

The first two instructions above are merely "dropping off" data for the adder to "chew" on, so to speak. They both take the minimal 10 ps (or whatever number that turns out to be).

Then, immediately AFTER the second instruction ends, the adder, now having two inputs to chew on, sets its ready bit to false and starts "chewing". It keeps its ready bit false for the duration, and sets it true again only when it has completed the calculation of its new sum.

At the same time, the third instruction starts to execute. Because slot 82's ready bit is now false, the main WIZ circuit's bus copy cycle must stop and wait. When the bit goes true again, the instruction continues again.

Devices like adders and multipliers can take hundreds of times longer than the minimal (10 ps) bus cycle. And their timing is variable. Multiplying two numbers may take longer than adding them. And adding a small number may take less time then adding a large number.

Thus each operation "takes as long as it takes".

And thus the instruction sequence is self-paced. Each instruction starts when the previous one ends.

Note also that without a clock running through everything, only those devices actually active use power. Every inactive slotted device uses zero power, and the main WIZ circuit, while waiting for a device (mid an instruction), also uses no power.