A note on interrupts - page 1

There is no WIZ circuit to support interrupts. The WIZ does not have "interrupts". It does not need to.

It is important to be reminded here that when a WIZ instruction reads a register that is not ready, the entire WIZ goes into a wait state. On a WIZ chip, that would be just one WIZ of many. As the frontend has no clock, when in a wait state not a single transistor in that WIZ switches and its power consumption goes to nearly absolute zero. (Some backend devices do run continuously, independent of the frontend -- but those are not relevant here).

Say we have a wire coming in to our chip and we want it to trigger some action when it goes high. On a traditional system, we connect this wire to an i/o port which is set to cause an "interrupt", and we then assign the address of some subroutine to be called when this trigger occurs, an "interrupt handler".

On the WIZ, we simply connect this wire to the ready bit of a register on some one WIZ, running some sequence which "handles" this register. When it executes this instruction:

   reg => X

if that wire is low, this instruction will put that WIZ into a zero-power wait state. It could sit there a moment, or a century. When the wire goes high, the ready goes high and the instruction completes and the sequence continues execution.

This is nothing new, it is the normal behavior of the WIZ. Just sayin'.