A note on interrupts - page 4

Here is a sequence which reads a series of samples (say from an A/D converter) and saves them in a 256-word circular buffer.

   sample => X
   buffer index , (1) => adder , (0xFF) => ander => buffer index
   X => buffer data
   (0) => repeat if zero

Here, the first instruction waits for the next sample. Its arrival wakes us from sleep. If samples come once a second or once a month, no matter. When one comes, we increment our index, modulo 256, and store our datum there.

So the essence of the situation is that any external signal which needs to be "handled" when it occurs, gets its own dedicated WIZ, and is connected to a register in it which causes a wait state when its ready bit is low.

Except that in the context of the WIZ, that is a silly statement, because *every* sequence gets its own WIZ, and *every* register causes a wait state when its ready bit is low.

So we haven't really said anything. We conclude that there is no need for interrupts: the situation they "handle" doesn't even exist.

Just sayin'.