Naked WIZes - page 2

Each of these single-operation functions would run on a WIZ with a multiplier or divider or whatever, directly on its bus. Plus a gateway and we have a four-register WIZ! (Three for the multiplier or a similar device, plus one for the gateway). We could use a 2-bit register address and a 4-bit instruction!! And note that its entire sequence is just three instruction long, eg "gateway=>adder, gateway=>adder, adder=>gateway", so perhaps just 4 bits per instruction x 3 instructions = 12 bits of program RAM in total!

Now let's imagine a WIZ with NO ARITHMETIC CAPABILITY AT ALL. It would have a const register set (to specify the WIZ IDs being called) and a gateway and nothing more!

Yet via that gateway it can access ANY function running on any of the other WIZes on the chip. Any program could be run on it, using nothing but function calls.

This is our "bare-naked" WIZ.

For non-speed-critical programs, this WIZ might be ideal. It could be implemented in a few thousand transistors, not 100,000 or 1 million as was used to estimate the number of WIZes that could fit on a single chip.

One can easily imagine a WIZ chip with a *huge* number of "naked" WIZes. The OS placement algorithm will no doubt instantiate lots of copies of these functions (like mult-funct, etc) in multiple WIZes distributed throughout the chip, perhaps one under every parent WIZ.