Instruction timing - page 2

Every backend device must provide two ready signals, read-ready and write-ready. These signals tell the frontend RCLs whether an instruction can proceed or not.

Simple devices like LEDs and switches, and very fast devices (eg the "ANDer"), are inherently faster than the bus cycle itself, and may be considered to be always ready. Also devices like boolean logic operations, shifts, branching tests (the conditional skip), etc, would generally be faster than the bus cycle. All of these would just tie their ready lines permanently high.

Thus our processor will exceed 100 GHz on all this class of instructions.

Only slower devices like adders and multipliers will need to generate a read-ready signal. They must set their readReady low the moment any of their inputs are changed, and high again only after completing the computation and writing the new output register bits.

Various devices can do this in various ways.

For example, our previously mentioned toggle switch was said to set readyReady only when the switch is flipped, and return to low right after the register was read. In that case, a read instruction would go into a zero-power wait until the switch was flipped.

Alternatively, that switch could tie readReady always high, and you could read it at any time, getting a 0 if off or a 1 if on. This would never produce a wait state.

Devices like adders and multipliers have a more complex determination. They must "know" when they are ready.