In the "What functions does a WIZ have?" chapter, I discussed how a WIZ-to-WIZ copy within a WIZ chip is similar to the across-chip bussing in an Intel or similar core. Thus, we only need a single WIZ within our chip to have a RAM which all other WIZes in the chip can then access.

We can also have multiple RAMs distributed around the chip. And/or some RAMs tied to single WIZes and not shared, if desired.

Note that we have a Harvard architecture. This RAM has nothing to do with the storage of program sequences. (See the "stored program" chapter.)

And finally, I will mention that our proposed operating system will add a software layer on top of the physical RAM to allow many other kinds of operations.