Here is what a register bit looks like. This is a classic textbook "D" flip-flop, with a tri-stated bidirectional i/o port. When EN-IN (enable input) is high, data flows from the bus to the D input of the bit. And when EN-OUT (enable output) is high, data flows from the Q output of the bit and onto the bus.

Note that this latch is wired to be self-clocking: the EN-IN signal that causes the D input to be driven also causes the EN input to go high. Setup and hold times are enforced by the RCL or register control logic, described very shortly.

The above is the classic structure. In the final VLSI implementation, the equivalent of this circuit can be implemented with just a few transistors.