To better coordinate the two WIZes and eliminate the races which could occur if both sides tried to write simultaneously, we can add two SR latches as shown above, (circled in red), which sit between the two register's RCLs and coordinate their ready bits.

The above circuit works like this: when B writes to the register, B cannot write again until A reads what B put there. This keeps B from writing a succession of datums too quickly. Thus there can be no "buffer overruns" because B simply cannot write to the buffer until A has read the prior data there. If it tries, it will go into a zero-power wait state until the write-ready line goes true again.

And not only can B not write again until A reads what it wrote, but B also cannot read the register until A writes some new data there for B to read. If B does try to read when there is no new data from A to read, B goes into a zero-power wait state until the read-ready line goes true again.

Note that this is asymmetric, with the A side more of a "master" and the B side more of a "slave". A symmetric version could just as easily be done, but the above version will come in quite handy when we talk about an OS running in WIZ A which controls processes running in WIZ B.