Here we show the top WIZ sharing three of its registers with one register each on three other WIZes, via gateways. We'll put the top WIZ on the "A" side of each gateway. I'll call it the "A-WIZ" and the other three "B-WIZes".

Suppose a cosine algorithm is running in one of the B-WIZes. It would look something like this:

   gateway => adder => multiplier => etc => etc => gateway

It picks up a number in its gateway, runs it through whatever computations are needed to compute a cosine, and then deposits the answer back into its gateway register.

Note that it has on its bus, in addition to a gateway to the A-WIZ, a number of other registers which would have things like adders, multipliers, etc, on their backend. Thus, the cosine computation would be able to run completely independently.

When it does its first instruction, "gateway => ", because of the gateway's ready bit configuration, if there were no datum waiting for it in its gateway, it would go into a zero-power wait state and sit idle until a datum arrived. Thus inactive functions use no power.

Now, suppose a main program were running in the top WIZ. At some point it might do:

   X => cosine  // write argument to gateway register shared with cosine WIZ

That would change the gateway's ready bits, the cosine WIZ would "wake up" and compute the cosine. At some point later the A-WIZ would do:

   cosine => Y  // get cosine answer to Y

If the cosine WIZ had not finished, that is, not deposited an answer back into its gateway register and thus setting the gateway's read-ready bit for the A-WIZ, this instruction would put the A-WIZ into a zero-power wait. Once cosine does finish, the instruction would proceed.

Now, with three B-WIZes, we could run any three functions in a similar fashion, all at the same time. For example, suppose we had a sequence running in the A-WIZ that will need cosine(a), sine(b), and sqrt(c) at some point within its computation. It would do, as early as possible (when a, b, and c were available):

   a => cosine ; b => sine ; c => sqrt
   ... the rest of the sequence ...

At some point in the sequence, one of the three functions will be needed. It does something like "sine => ...". At that point a wait may occur. Eventually the sine algorithm will finish and the A-WIZ sequence will continue. Later, if the cosine answer is needed, if the cosine algorithm is faster than the sine, there will be no wait, as the cosine WIZ was also running while we were waiting for the sine. Of if the cosine algorithm is slower, we will wait, but only for the time difference between the two algorithms.

No matter what order they are used, the total time they add to the entire sequence will be just the delay of the slowest of the three.

In reality, the above is a poor architecture. None of the B-WIZes can call each other, and if the A-WIZ needs a fourth B-WIZ? There is no flexibility. A much more generalized structure is shown in the next chapter. But the main idea is the same.