My apologies: this drawing needs to be re-drawn. It is functionally correct, just not very "pretty". The "internal program memory" needs to be right above or next to the Executor, because it is almost a part of it, but selected out by a mux to the OS-WIZ if desired.

In other words, the Executor is normally fed by the Internal Sequence Memory, but with a mux in the path so that the internal memory can be switched out and replaced by a direct path to the OS-WIZ.

At power-on boot, the mux is set to take data from the OS-WIZ. Thus the parent (OS) WIZ can literally "force feed" instructions to its child WIZes. It merely writes an instruction and that instruction is executed.

The OS passes enough instructions through to load the internal memory with an initial sequence. Then it flips the switch and allows the memory to drive execution from that point on.

This same technique can be used at a later time to stop, change, or start new sequences.

Note that since every WIZ has its own sequence memory, and generally that memory would be much faster than any "L1" memory on traditional machines, and because there is no conflict between WIZes as no sequence memory is shared, the whole concept of instruction "cache" is simply gone.

Now data RAMs are another story (see "RAM" chapter). These would not be used for program memory, and might often have their own internal cache for commonly used data.

Simple enuf, eh?