We will shortly look at the WIZ chip in detail, with as many as a million individual WIZes in it, and a very fast inter-WIZ communication cycle. And we are going to introduce an operating system which splits programs up into small blocks, and loads each block into separate WIZes. Consider this example, in pseudo-code:

   if (X > 12*Y) then { C -> D; E -> F; } else { G -> H; I -> J; }

This would be treated as if it were like this:

   if (X > 12*Y) then block1-funct() else block2-funct();
   ...
   define block1-funct() { C -> D; E -> F; }
   define block2-funct() { G -> H; I -> J; }

This would run in three different WIZes, one to execute the main line, and one each to execute the two block functions.

The main line WIZ would need a multiplier on its backend in order to handle the "12*Y", and a skip register and an adder to handle the ">". The WIZes running the two block functions require no arithmetic capability at all, and just two 16-bit words of sequence memory. These could both run on what I call a "bare-naked" WIZ, a WIZ with practically no backend circuits at all, and a very small sequence memory.