A typical Intel microprocessor core might have say four FPUs (Floating Point Units). A WIZ chip with just four of its WIZes (out of a million) with similar FPUs on their buses would have the same computational power.

The Intel core has a number of internal busses which move data around, including to the four FPUs. A WIZ chip has an internal fabric which enables communications from any WIZ to any other WIZ on the chip, including to any of the four WIZes with FPUs on their backend. In terms of speed and efficiency, these would be about equivalent.

Following up on this idea, one could easily imagine just a few WIZes in a WIZ chip with *ANY* particular function, and then a host of WIZes without that function, but still able to access that function via inter-WIZ function calls.

This would apply to algorithms as well. For example, if just one WIZ on the entire chip had the wherewithal to do fast Fourier transforms (say 64 fast multipliers and 64 fast adders and such, directly on its backend), then every other WIZ on the chip could "call" it.

On the other hand, we could also easily imagine the opposite: a chip with 100,000 WIZes indentically configured, each with 256 vector dot product devices on their backends, and all running simultaneously. That's 256 million dot products at once. This would be a massively parallel chip useful for AI, computer graphics, and more.