The transition from ZOZ to WIZ - page 4

It is expected that sequences which do nothing but generic arithmetic computations will be extremely common. And it is expected that WIZes with many generic computational objects will be manufactured. In these cases, we can expect to see a 100% conversion from long ZOZ instructions to short WIZ instructions.

Essentially this corresponds to a run-time compilation down to native WIZ machine instructions. Such sequences will then run extremely rapidly and efficiently.

The second most commonly expected situation would be an instruction which calls another sequence ("subroutine") on the same chip.

As described in chapter "A chip full of WIZes", we have can have as many as 2^32 or about 4 billion WIZes on one chip. (If Moore's Law holds, it will be the year 2060 until that becomes a limitation). Every one of these WIZes has a long ZOZ serial number, but we can also assign each a shorter 32-bit "WIZ ID".

As described in that same chapter, the "fabric" of a WIZ chip is (or could be) a hierarchy of WIZes, 256 WIZes to a parent WIZ, 256 parent WIZes to a grand-parent WIZ, etc. We have also defined a protocol for inter-WIZ communication, which specifies that a WIZ delivers a 32-bit WIZ ID to its gateway, followed by one or more 32-bit words of data to be sent to that given WIZ.

Thus, when an instruction occurs of the form

   xxx -> 938474499823.  // long ZOZ serial number

And that given WIZ is on the same chip as xxx, we can map that to:

   xxx -> WIZ-ID.        // (32 bits)

And this can be executed via our gateway-to-parent protocol as:

   <WIZ-ID> -> gateway ; xxx -> gateway

Here, the OS running in the parent picks up the ID and data and drops it off at the gateway of the addressed WIZ, or uses the same protocol to pass it on further to the grand-parent WIZ, etc.